1. Field of the Invention
The present invention relates to a high speed memory access circuit of a CRT display unit. More particularly, the present invention relates to a high speed memory access circuit to be utilized in a raster scan type color graphic display unit, by which high speed access is applied to a frame memory where pattern data is stored.
2. Description of the Prior Art
FIG. 1 is a schematic block diagram of a conventional color graphic display unit which provides a background to the present invention. First, referring to FIG. 1, the operation of a conventional raster scan type graphic display unit will be briefly described. Data is supplied from a host computer 1 to a pattern data control portion 3 through a transmission line and a host interface 2. The pattern data control portion 3 receives the data from the host computer 1 and arranges the data as a pattern to be displayed so that the data arranged as a pattern is stored in a segment buffer, not shown. A data analytic portion 4 takes out the content of the segment buffer and analyzes the data whereby vectors are calculated based on start point coordinates and end point coordinates. Then, in case of applying extension, reduction, rotation, parallel movement and the like to a pattern, a coordinate conversion clip portion 5 multiplies the data by necessary matrices. In a case where a portion of a pattern on the screen of a CRT display unit is bounded by border lines, the portions protruding from the border lines are clipped off by the coordinate conversion clip portion 5.
In the case of painting out a pattern, a DDA control paint portion 6 provides decomposed line segments existing inside the coordinates of the vertexes of the respective vectors whereby data for painting out is obtained. A DDA 7 is a straight line generating circuit, which calculates coordinates of intermediate points of a vector connecting a start point and an end point based on the data from the DDA control paint portion 6 and develops the result of calculation in the frame memory 8 to obtain a straight line. The frame memory 8 stores the dots on the straight line generated by the DDA 7. The data stored in the frame memory 8 is supplied to a video control portion 9 so that the data is converted into an analog signal by D/A conversion and is also converted into a video signal based on a color conversion table so as to be supplied to a color monitor 10. As a result, in the color monitor 10, a pattern based on the data provided from the host computer is displayed.
FIG. 2 is a block diagram showing the frame memory 8 shown in FIG. 1 and peripheral circuits thereof; FIG. 3 is a diagram showing a composition of a screen in a color monitor; and FIG. 4 is a timing chart for explaining the operation of the frame memory shown in FIG. 2.
Now, referring to FIGS. 2 to 4, a more detailed description will be made of the operation of the frame memory 8 shown in FIG. 1. The color monitor 10 is composed of 1280 bits as the X coordinates and 1024 bits as the Y coordinates as shown in FIG. 3. For this purpose, dynamic random access memories (hereinafter referred to as D-RAM's) 81 to 86 of 64K bytes are employed as shown in FIG. 2. As address signals, X read address signals SAX 5 to 10, Y read address signals SAY 0 to 9, X write address signals WAX 5 to 10 and Y write address signals WAY 0 to 9 are applied to an address multiplexer 11. The address multiplexer 11 applies, based on a RASAD signal provided from a memory cycle controller 14, address signals AD 0 to 7 to the D-RAM's 81 to 86 at the time of reading and writing of the data.
WAX 2 to 4 form the lower three bits of the write address signals and are supplied to a chip selection decoder 12. The chip selection decoder 12 supplies, based on the singals applied thereto, chip selection signals CS 0 to 5 for selection of any one of the six D-RAM's 81 to 86 to the memory cycle controller 14. The write data WD 0 to 3 of 4 bits are supplied to a read modified write gate 13. The read modified write gate 13 performs a read modified write operation and determines write data Di 0 to 3. More specifically, when the write data WD0 to 3 are applied to the read modified write gate 13, the read modified write gate 13 supplies the write data Di 0 to 3 to the D-RAM's 81 to 86, assuming a proper relation with the output data Do 0 to 3.
The memory cycle controller 14 determines a memory read cycle in synchronism with a horizontal synchronizing signal RESYNC and determines a write cycle by a write signal STORE provided from the exterior. Subsequently, address control signals RAS 0 to 5 and CA 0 to 5 and write enable signals WE 0 to 5 are supplied to the D-RAM's 81 to 86 respectively, and a load signal LD is supplied to a parallel load shift register 15.
Now, referring to FIG. 4, the operation of the frame memory 8 shown in FIG. 2 will be described. At the time of writing, the Y direction is addressed with 8 bits of the Y write address signals WAY 2 to 9 according to the timing of descent of the address control signal RAS, and the X direction is addressed with 8 bits of the X write address signals WAX 5 to 10 and the Y write address signals WAY 0 and 1 according to the timing of descent of the address control signal CAS. Then, the 4-bit write data WD 0 to 3 are processed by read modified write to have a proper relation with the read out data Do 0 to 3 and the 4-bit data Di 0 to 3 are written in the D-RAM's 81 to 86.
At the time of reading, the Y direction is addressed based on the 8-bit Y read address signals SAY 2 to 9 according to the timing of descent of the address control signal RAS, and the X direction is addressed based on the 8 bits of the X read address signals SAX 5 to 10 and the Y read address signals SAY 0 and 1 according to the timing of descent of the address control signal CAS. As a result, data of 24 bits in all, namely, 4 bits from each of the D-RAM's 81 to 86, are read out at a time and supplied to the parallel load shift register 15. The parallel load shift register 15 loads in parallel the 24 bits of data from the D-RAM's 81 to 86 in response to the load signal LD from the memory cycle controller 14. Then, the data are shifted by the clock pulses of a predetermined video scanning frequency to be provided as serial data.
In a such a color graphic display unit as structured above, the video scanning frequency is defined by the memory cycle of the D-RAM's 81 to 86. The access speed of a D-RAM currently in use is limited to the video scanning frequency band 55 MHz and such D-RAM's cannot meet the conditions of a CRT display unit of a 60 Hz non-interlace system requiring 100 MHz or more. In addition, as for the parallel load shift register 15 for shifting a read signal, an inexpensive integrated circuit operable with a frequency band of 100 MHz does not exist at present and some measures will need to be taken in this point. Moreover, for high speed writing into the frame memory 8, it is necessary to increase the number of bits for simultaneous writing since there is a limitation on the memory cycle of the D-RAM's 81 to 86. For this purpose, it is necessary to consider an efficient structure of writing areas.